- Perform design implementation from RTL to GDS which includes RTL synthesis, Timing constraints creation, Static Timing Analysis, SCAN insertion and ATPG, Chip floor plan, Timing Driven Placement & Route, and Power Analysis.
- Improve efficiency and reliability of backend flow.
- Postgraduate degree or above in Electronic Engineering or Computer Engineering or equivalent.
- At least 2 years relevant experience.
- Familiarities / knowledge in display driver IC development or low power design development would be considered as an advantage.
Please send a detailed resume with expected salary to [email redacted, apply via Jobable]. Please quote our reference number in your application.
All applications will be treated in strict confidence and for recruitment purpose only.
Only short-listed candidates will be notified.