- Algorithm Design
- Corporate Communications
- Perl Programming
Senior Engineer/Engineer, ASIC Design
- Carry out research on new technologies in IC design
- Carry out logic design, module-level or top-level verification
- Research in latest Digital Communications or Cryptography and applications
- Bachelor’s Degree in Electronic Engineering/Electrical Engineering/Information Engineering/IC Design or related fields with 6+ years’ experience, or Master’s Degree with 3+ years’ experience, or PhD holder in related area. Candidates with less experience will be considered as Engineer
- Hands-on experience in micro-architecture, RTL coding, logic synthesis, functional verification, formal verification and timing analysis
- ASIC Design experience in Digital Communications or Cryptography is preferred
- Algorithm Design experience in Matlab/C in Digital Communications of Cryptography is preferred
- System Verilog verification experience is preferred
- FPGA prototyping and ASIC bring up experience is preferred
- Good in Unix/Linux, and script writing skills in Perl, Cshell, and/or tcl
Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.
Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email (preferable) or post no later than : 30 October 2016
Email: [email protected]
Post: 5/F, Photonics Centre, 2 Science Park East Avenue,
Hong Kong Science Park, Shatin, Hong Kong.
Only short-listed candidates will be notified. Personal data provided by applicants will be used for recruitment purposes only.
|Career Level||Senior (6-10 years)|