Senior Engineer, ASIC Design for Communication Systems
- Carry out design and RTL implementation of integrated circuits for communication systems.
- Execute module level and system level verification.
- Perform logic synthesis and timing analysis.
- Carry out ASIC or FPGA implementation.
- Bachelor’s degree or above in Electronic Engineering or equivalent;
- Bachelor’s degree with 6+ years working experience; Master’s degree with 3+ years working experience; Fresh Ph.D would also be considered;
- Hands-on experience in RTL coding, logic synthesis, functional verification, formal verification and timing analysis
- Design experience of digital communication systems such as LTE-Advanced/LTE, HSPA/WCDMA/TD-SCDMA, ZigBee, Bluetooth and WiFi is a plus;
- Good team player with excellent communication skills.
- Less qualified candidates can be considered to offer with lower level.
Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.
Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email (preferable) or post no later than 30 October 2016.
Email: [email protected]
Post: 5/F, Photonics Centre, 2 Science Park East Avenue,
Hong Kong Science Park, Shatin, Hong Kong.
Only short-listed candidates will be notified. Personal data provided by applicants will be used for recruitment purposes only.