- Perl Programming
Senior Engineer, ASIC Design
- Carry out research on new technologies in IC design.
- Carry out micro-architecture design, HDL coding, logic synthesis and timing analysis for digital circuit.
- Carry out module-level or top-level functional verification and FPGA prototyping.
- Interface with backend design team for physical implementation.
- Use various lab instrument, such as oscilloscope, signal generator, etc., to perform PCB prototype verification, testing and trouble shooting.
- Bachelor’s degree with 6+ years of experience, or Master’s degree with 3+ years’ experience, or PhD holder. Candidates with less experience will be considered as Engineer.
- Hands-on experience in micro-architecture, RTL coding, logic synthesis, functional verification, formal verification and timing analysis.
- Experience in FPGA prototyping and IC tapeout is preferred.
- Lab experience in bringing up silicon sample is preferred.
- Familiar with SoC design methodology and latest EDA tools (such as Cadence, Synopsys and Mentor Graphics).
- Good in Unix/Linux, and script writing skills in Perl, Cshell, and/or tcl.
Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.
Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email (preferable) or post no later than 30 October 2016.
Email: [email protected]
Post: 5/F, Photonics Centre, 2 Science Park East Avenue,
Hong Kong Science Park, Shatin, Hong Kong.
Only short-listed candidates will be notified. Personal data provided by applicants will be used for recruitment purposes only.
|Career Level||Senior (6-10 years)|