- Algorithm Design
- Corporate Communications
- Perl Programming
Principal Engineer/Senior Engineer, ASIC Design
- Carry out research on new technologies in IC Design;
- Carry out micro-architecture design, RTL coding, Logic synthesis and timing analysis for digital circuit;
- Carry out Algorithm Design;
- Carry out module-level or top-level verification.
- BSEE or equivalent education with 10+ years experiences / MSEE or equivalent education with 8+ years of experience / PhD or equivalent education with 5+ years of experience in digital IC design;
- Hands-on experience in micro-architecture, RTL coding, logic synthesis, functional verification, formal verification and timing analysis;
- ASIC Design experience in Digital Communications or Cryptography is preferred;
- Algorithm Design experience in Matlab / C in Digital Communications or Cryptography is preferred;
- System Verilog verification experience is preferred;
- FPGA prototyping and ASIC bring up experiences is preferred;
- Good in Unix / Linux, and script writing skills in Perl, Cshell, and/or tcl;
- Team player and strong communication skills.
- Candidate with less experience may be considered for position of Senior Engineer.
Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.
Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email (preferable) or post no later than 30 October 2016.
Email: [email protected]
Post: 5/F, Photonics Centre, 2 Science Park East Avenue,
Hong Kong Science Park, Shatin, Hong Kong.
Only short-listed candidates will be notified. Personal data provided by applicants will be used for recruitment purposes only.
|Career Level||Lead (more than 10 years)|